Which is your Holy Grail of CPU collecting?
i4004 with grey traces
AMD K6 black top
NexGen Nx686
Cyrix MII 433
Winchip 3
Other, Mail me!

View Current Poll
View All Polls
CPU Collection Info

Total of CPU´s :
Warning: mysql_result() expects parameter 2 to be long, string given in /home/cpuinfo/public_html/html/addinfo.php on line 28

Total in Tradelist :
Warning: mysql_result() expects parameter 2 to be long, string given in /home/cpuinfo/public_html/html/addinfo.php on line 30




NexGen Nx586 - Designing the impossible?

NexGen wanted to design a high performance CPU using techniques that were new in the x86 processor business. Compatibility with the x86 instruction set was one of the highest priorities. Much time went into finding out exactly what x86 meant as Intel's documentation wasn't always clear or complete. So a lot of testing was done to ensure compatibility.

Early samples, these were manufactured by Yamaha, consisted of 8 separate chips. Production techniques at the time were not advanced enough to produce the design in a single chip. There was the Instruction Decoder chip (DEC), Adress Preparation processor (AP), Integer Execution Unit (IEU), Numerics processor (NP), Memory and Cache controller (MCC), Instruction Tag chip (ITAG), Data Tag chip (DTAG) and Bus interface (BU).

The first tape outs contained many bugs, these were corrected in different ways. Sometimes the bug could be corrected using hypercode to emulate the correct actions. Other bugs had to be fixed by changing the actual chip design. Some bugs were even left in the design as the possibility of an occurrence was very unlikely.

From the start of the design in 1986 there was the idea of using RISC like instructions instead of the normally used CISC instructions in x86 CPU's. This was something no other x86 CPU manufacturer had done before, NexGen was doing something completely new! It can best be described like this; the software talks to the CPU in CISC instructions, the CPU translates these into RISC instructions and carries them out. The results are translated back from RISC to CISC and are communicated with the software (very simple explanation for something very difficult!). These RISC like instruction were implemented in the form of pseudo-operations or P-ops in the NexGen design. When Dave Epstein became Vice President of Engineering, he named the P-ops RISC86 as a slick way of describing the internal opcodes.


Dave Epstein also gave the NexGen design a codename : F86. One engineer remembered he was told it meant "Fast x86".


Previous page
Next page

Contact us
All trademarks used on this site are properties of their respective owners.
Copyright © 2000-2006 WWW.CPU-INFO.COM